• Location: Hanoi / Ho Chi Minh City, Vietnam
• Work Mode: Flexible Working Hours / Dynamic Environment
• Experience Level: 2+ - 10+ years
• Industry: Semiconductors / VLSI

Job Summary

We are seeking a Design Verification Engineer to play a pivotal role in ensuring the functional correctness of next-generation ASIC/SoC designs. In this role, you will combine your technical expertise in UVM/SystemVerilog with leadership capabilities—providing technical solutions, mentoring junior team members, and driving verification closure from initial test planning through to successful tape-out.

Key Responsibilities

1. Technical Leadership & Guidance

• Act as a technical anchor within projects, providing robust solutions and guiding technology execution to ensure successful work completion.
• Mentor and develop team members to enhance their technical capabilities, engineering best practices, and overall productivity.
• Actively participate in, or lead, technical discussions and design/verification reviews to ensure module-level process compliance.

2. Verification Strategy & Environment Development

• Develop, maintain, and modify comprehensive full-chip and subsystem-level verification test plans.
• Architect and enhance advanced testbenches using SystemVerilog (SV) and OVM/UVM methodologies.
• Code, execute, and debug complex test cases, managing regression suites and identifying underlying design bugs.

3. Execution, Signoff & Risk Management

• Perform detailed coverage analysis (functional and code coverage) to drive verification closure.
• Execute Gate-Level Simulations (GLS) to validate design behavior under real-world timing conditions.
• Prepare and submit detailed project status reports to minimize risk exposures, manage project timelines, and resolve technical escalations efficiently.

Required Skills & Qualifications

• Education: Bachelor’s degree in Electronics Engineering, Electrical Engineering, or a related equivalent discipline.
• Experience: 2+ years of proven experience as a Design Verification Engineer.
• Methodologies & Languages: Deep understanding of the ASIC/SoC lifecycle with hands-on expertise in OVM/UVM architectures using SystemVerilog.
• Protocols & Standards: Solid familiarity with prevalent industry protocols such as PCIe (Gen 3/4/5), USB3, DDR4/5, Ethernet, CSI2, I3C, or AMBA.
• Simulation & Verification Tools: Strong experience in testbench development, regression management, bug analysis, and Gate-Level Simulations (GLS).
• Automation: Proficiency in scripting languages for verification environment automation and optimization.
• Track Record: Must have participated in multiple ASIC/SoC verification cycles leading up to the tape-out stage.
• Soft Skills: Good command of English with strong cross-functional communication and reporting skills.

What We Offer (Benefits & Perks)

• Financial Security: 100% full salary and benefits from your very first day, a 13th-month salary, and an insurance plan based fully on your gross salary.
• Premium Healthcare: Comprehensive medical benefit package covering both the employee and their immediate family members.
• Allowances & Workplace Perks: Monthly meal allowance of 730,000 VND, along with free snacks, refreshments, and free parking at the office.
• Work-Life Balance: Friendly working environment with highly flexible working hours and a culture centered on trust.
• Generous Time Off: 18 paid leaves per year
• Global Exposure: Opportunities for international travel and onsite assignments across 49 countries.
• Continuous Learning: Robust internal technical, functional, and professional English training programs designed to keep your skills at the industry forefront.
• Top-Tier Talent Network: Collaborate daily with outstanding, like-minded colleagues coming from top universities and leading global tech firms.

About the Client

Our client is an established global technology leader specializing in engineering, digital innovations, and advanced semiconductor solutions. Boasting a massive multinational footprint, they collaborate with top-tier universities and industry-leading enterprises worldwide. For engineers looking to push the boundaries of silicon validation, they offer a highly collaborative, fast-paced ecosystem to work on complex ASIC/SoC architectures up to the tape-out stage.